1. Field of the Invention
The present invention relates to computer systems which include devices having different data widths, e.g. 32 and 64 bit devices. More specifically, the invention includes logic which allows a device, having a smaller data width than the system bus and the central processing unit (CPU), to be directly attached to the system bus and transparently interact with the CPU.
2. Description of Related Art
Currently, techniques are known which allow a system to address memory locations in order to support a plurality of different predetermined sized memory modules. For example, U.S. Pat. No. 4,908,789 uses four high order address bits that are converted to 16 sequentially ordered segment lines. Combinational logic then processes each segment line to develop memory bank select signals in accordance with the size signals obtained from the memory modules. Additionally, European Patent Application 0 382 358 translates address between 24 and 32 bit memory addresses by using a direct memory access controller which can provide both a 32 and 24 bit memory address operation. A byte pointer is used in conjunction with an I/O port to provide information to the DMA controller. The byte pointer counts as each byte of information is provided such that is only 3 bytes are received the system knows that a 24 bit operation is occurring.
U.S. Pat. No. 4,933,846 uses an interleaved memory with two 16 bit buses to allow 16 bit devices to be attached across either a first or second 16 bit bus (but not both), and 32 bit devices are attached across both 16 bit buses. The 32 bit devices use both common 16 bit buses, while the 16 bit devices use only their dedicated common 16 bit bus.
Additionally, some conventional systems allow microprocessors to be coupled to peripherals having different data widths. U.S. Pat. No. 5,075,969 is an improvement in a microprocessor wherein a specialized function provides address signals for an n byte transfer of data. Input means receives a byte size signal which indicates the number of bytes that will be transferred on the next ready signal. Output means provide a signal indicating that a data transfer request by the microprocessor will be satisfied with the data transfer occurring at the next ready signal. It can be seen that this system requires modification of the microprocessor to account for these signals. Further, the microprocessor must participate in the data transfer such that the data transfer is not transparent.
U.S. Pat. No. 5,191,653 describes a bi-directional bus adapter which couples a system bus and an I/O bus. A mechanism is included for routing data between the system and I/O buses such that the data path directs bytes of data to specific data lines to perform byte steering and dynamic bus sizing. A plurality of devices having different bus widths are connectable to a system bus via the bi-directional bus adapter, however, this system does not support the ability of a device having a data width different from the system bus width to be attached directly to the system bus.
IBM Technical Disclosure Bulletin, vol. 33, no. 2, July 1990, pages 38-39, describes a method of providing data steering for a 32 bit memory slave so that it can run in either a 16 bit or 32 bit I/O bus.
None of these conventional systems provide the ability to transparently attach a device having a data width different from the system bus directly to the system bus. Conventional solutions include translated memory addresses, modifying the microprocessor to take into account devices with different data width, or adding an adapter. Thus, it would be advantageous to have a system that will allow devices of differing data widths to be directly attached to the system bus, without requiring any modification of the CPU, or the addition of a bus interface adapter.